Job Overview:

We are looking for an experienced ASIC RTL Design Engineer to join our team and contribute to the design, development, and implementation of next-generation SoC/IP solutions.

Key Responsibilities:

• RTL design & micro-architecture development (Verilog/System Verilog)
• End-to-end ASIC front-end flow: spec → RTL → synthesis → STA support
• Block/IP integration, lint/CDC, timing & power optimization
• Debugging, simulation, and cross-functional collaboration with DV/PD/DFT teams

Qualifications & Requirements:

• Bachelor’s degree in computer science, Electrical/Electronics Engineering, or a related field. OR
• Master’s degree in computer science, Electrical/Electronics Engineering, or a related field. OR
• PhD in Computer Science, Electrical/Electronics Engineering, or a related field.
• Strong digital design fundamentals
• Hands-on experience with ASIC flows & EDA tools (DC, VCS/Xcelium, SpyGlass)
• Knowledge of bus protocols (AXI/AHB/PCIe/DDR)
• Scripting (Python/TCL) is a plus