DFTStreamlining Success: DFT for Seamless Functionality

Our DFT team works very closely with your Product Engineering teams to identify the product market for cost, quality and reliability. Then we architect DFx (which is DFT, DFM, DFD) to meet you product post silicon manufacturing, product life cycle to manage quality and debug. Then we would work with the RTL teams to first evaluate the RTL to meet the product goals. We would then define additional DFT to make sure we meet the Testability goals. Then the DFT team will design all the Test controllers as defined by the architecture including Test instruments for combinatorial logic including compression engines, LBIST, MBIST, SERDES PRBS. We would also check the RTL and propose RTL DFT fixes to meet the test coverage or test cost issues. We would also define and insert additional test mode controllers if burnin or in-system tests are required. We would then do scan, MBIST, PLLBIST and I/O BIST insertion and verification and generate the physical design ready netlist, with all the collaterals required for physical design.
In addition, the DFT team works with the physical implementation team to ensure that during the implementation phase all clocking, timing, connectivity and congestion are accounted for. We would also work with the Post-silicon Test Engineering and Product engineering teams to provide them with the data required for designing their load boards, test programs etc. We will work with Post-Silicon product engineering to ensure that the part will be first time silicon success. We would work with the product engineering team to ensure that we can meet their HTOL, Burnin, characterization requirements in addition to the scan/memory patterns delivery. We will work with the product engineering team to debug and diagnose design errors to yield limiters and quickly fix the design so that the product will reach volume production in the quickest time. Our team will work with you full end to end specification to volume production in the shortest time possible.

Eximietas offers a complete suite of DFT services as below but not limited to the following:

  • DFx architecture for SoC to chiplets to SiP.
  • Work with product engineering to plan the manufacturing flow.
  • Work with external IP vendors to integrate their IP test and DFT into manufacturing flow.
  • Execute hierarchical scan insertion flow. Run ATPG to ensure coverage goals are meet.
  • Logic BIST, X-bounding, test-isolation, validate the LBIST patterns.
  • Memory BIST with memory redundancy/repair plan.
  • Boundary Scan Insertion with test pin sharing to enable ATE mapping of pins to have the most optimal structural test.
  • Test data volume and Test cost using compression engines, repeated block sharing, SSN controllers and high speed I/O test access to optimize test cost.
  • Work with the design teams to ensure that we address multiple power, test power and employee techniques to meet the product power requirements for test.
  • Work with the product teams to ensure HSIO test is planned with different loopbacks (internal, pad, near-end and far-end).
  • Fault Simulation of the custom circuits or functional patterns to get credit for the patterns run during manufacturing